Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Software and hardware “tools” then verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows. First, the specifications for the new microcircuit are described in terms of logical operations, typically using a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). After the accuracy of the logical design is confirmed, the logical design is converted into device design data by synthesis software. The device design data, in the form of a schematic, represents the specific electronic devices, such as transistors, resistors, and capacitors, which will achieve the desired logical result and their interconnections. Preliminary timing estimates for portions of the circuit may also be made at this stage, using an assumed characteristic speed for each device. This schematic generally corresponds to the level of representation displayed in conventional circuit diagrams.
Once the relationships between circuit devices have been established, the design is again transformed into physical design data describing specific geometric elements, often referred to as a “layout” design. These geometric elements (typically polygons) define the shapes that will be created in various materials to form the specified circuit devices. Custom layout editors, such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for this task. Automated place and route tools also will frequently be used to define the physical layouts, especially the placement of wires that will be used to interconnect the circuit devices. Each layer of the microcircuit will have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device. For example, the shapes in the representation of an implant layer will define the regions where doping will occur, while the shapes in the representation of a metal layer will define the locations of metal wires used to connect the circuit devices. Thus, the layout design data represents the patterns that may be written onto masks used to fabricate the desired microcircuit during a photolithographic process.
Modern integrated circuits typically will be formed of multiple layers of material, such as metal, diffusion material, and polysilicon. During the manufacturing process, layers of material are formed on top of one another sequentially. After each layer is created, portions of the layer are removed to create circuit element structures. Together, the circuit element structures form the operational circuit devices which make up the integrated circuit, such as transistors, capacitors and resistors. Before a new layer is formed over the circuit element structures in an existing layer, however, the existing layer must be polished to ensure planarity. Polishing, using any of various types of polishing processes, is sometimes generically referred to as “planarization.”
One problem with conventional planarization methods is that different materials will have different densities, so softer materials will be polished more than harder materials. As a result, a layer's surface may become uneven, causing the next layer to have an uneven surface as well. If this occurs, upper (i.e., subsequently formed) layers of material will have a very irregular surface topography. Such irregular surface topographies may cause a variety of flaws in a circuit device, such as holes, loss of contact, and other defects.
To improve the planarity of a layer of material, the integrated circuit designer (or manufacturer) often will analyze the layout circuit design for the layer to identify empty regions. For example, the designer or manufacturer may analyze the design of the layer to determine the density of the functional structures that will be formed in the layer, and identify regions that are empty of these functional structures. The designer or manufacturer will then modify the layout circuit design to fill these empty regions with data representing “dummy” or “fill” structures. That is, the designer or manufacturer will modify a design to increase the density of structures that will be formed in the layer. When the circuit is manufactured, these “dummy” or “fill” structures will be formed alongside the “functional” circuit element structures (i.e., the structures used to form functional circuit devices), so that the overall surface of the layer is more consistently flat. This type of corrective technique may be implemented using a software application for identifying and manipulating structures defined in a layout circuit design, such as one or more tools in the CALIBRE® family of software tools available from Mentor Graphics® Corporation of Wilsonville, Oreg.
While this corrective technique often improves the planarity of layers in an integrated circuit, it has some drawbacks. For example, fill structures that are not electronically coupled to an interconnect (e.g., a signal line or wire) or other functional circuit structure can be automatically generated when the circuit design is finalized. These “floating” fill structures will significantly increase the coupling capacitance between adjacent interconnects, however, which in turn may create unwanted crosstalk between adjacent interconnects. These “floating” fill structures may also increase the total interconnect capacitance for the layer.
On the other hand, if a fill structure is electrically coupled to an interconnect, then this “grounded” fill structure may significantly increase the interconnect's total capacitance. This increased interconnect total capacitance in turn may affect the delay of signals carried by the interconnect. Thus, if the designer or manufacturer inadvertently fills too much of the empty regions with grounded fill structures, the increased capacitance in the manufactured device may cause one or more of the circuit devices to exceed their minimum timing requirements. In addition, “grounded” fill structures must be routed like the interconnects, creating further complexity for the circuit design.
To address these deficiencies, various fill techniques have focused on manipulating the shape of the fill structures, or their placement relative to other functional structures in a layer of a circuit. For example, some techniques may place long fill structures parallel to interconnect lines, while other techniques may place fill structures orthogonal to interconnect lines. While a variety of fill techniques have been proposed, there is still a continuing desire to be able to add fill structures to a circuit while curtailing the amount of additional capacitance created by the additional fill structures.